Invention Grant
US06498092B2 Method of making a semiconductor device having dual damascene line structure using a patterned etching stopper
失效
使用图案化蚀刻阻挡件制造具有双镶嵌线结构的半导体器件的方法
- Patent Title: Method of making a semiconductor device having dual damascene line structure using a patterned etching stopper
- Patent Title (中): 使用图案化蚀刻阻挡件制造具有双镶嵌线结构的半导体器件的方法
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Application No.: US09780830Application Date: 2001-02-09
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Publication No.: US06498092B2Publication Date: 2002-12-24
- Inventor: Kyung-tae Lee , Seong-ho Liu
- Applicant: Kyung-tae Lee , Seong-ho Liu
- Priority: KR00-42750 20000725
- Main IPC: H01L214763
- IPC: H01L214763

Abstract:
A semiconductor device having a dual damascene line structure and a method for fabricating the same are disclosed. The semiconductor device and the method solve the conventional problem of a partially, or fully, closed contact hole, and restrain increase in the parasitic capacitance in an interlayer insulation layer due to an increase in the dielectric constant thereof through the use of an etching stopper layer. To achieve this, a first interlayer insulation layer is formed on a semiconductor substrate on which a first conductive pattern is formed. Next, the etching stopper pattern having an etching selection ratio with respect to the first interlayer insulation layer is partially formed in a particular area. Thereafter, a second interlayer insulation layer and a second conductive layer made of copper are formed.
Public/Granted literature
- US20020030280A1 Semiconductor device having dual damascene line structure and method for fabricating the same Public/Granted day:2002-03-14
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