A Circuit for conditioning sync signals for devices for the line-by-line Display of video signals includes, a first input for horizontal sync signals (H1sync, H2sync), a second input for vertical sync signals (Vsync), and a delay stage. The delay stage outputs a signal (Vshift) which is delayed relative to the vertical sync signal (Vsync) by a specific delay time (reg). The circuit determines the timing of the horizontal sync signals (H1sync, H2sync) relative to the vertical sync signal (Vsync) and/or relative to the delayed signal (Vshift). The delay stage is designed in such a way that the delay time (reg) is adjustable.