发明授权
US06498822B1 Frequency and timing synchronization circuit making use of a chirp signal 失效
频率和定时同步电路利用啁啾信号

  • 专利标题: Frequency and timing synchronization circuit making use of a chirp signal
  • 专利标题(中): 频率和定时同步电路利用啁啾信号
  • 申请号: US09295395
    申请日: 1999-04-21
  • 公开(公告)号: US06498822B1
    公开(公告)日: 2002-12-24
  • 发明人: Hiroshi Tanaka
  • 申请人: Hiroshi Tanaka
  • 优先权: JP10-129699 19980424
  • 主分类号: H04L700
  • IPC分类号: H04L700
Frequency and timing synchronization circuit making use of a chirp signal
摘要:
To surely detect a frequency shift and a timing difference of a received signal making use of a chirp signal even when the C/N ratio of the received signal is low by resolving the problem of resolution of FFT processing, a frequency and timing synchronization circuit comprises: a chirp signal generator (6) for generating a reference chirp signal and a conjugate complex signal of the reference chirp signal; a first demodulator (7) for obtaining a first in-phase complex signal and a first quadrature-phase complex signal by demodulating the received signal with the reference chirp signal and the conjugate complex signal a frequency offset circuit (5) for obtaining an offset signal by shifting a frequency of the received signal; a second demodulator (8) for obtaining a second in-phase complex signal and a second quadrature-phase complex signal by demodulating the offset signal with the reference chirp signal and the conjugate complex signal; and a detector unit (9) for detecting the frequency shift and a difference of the synchronization timing according to a first peak frequency giving a maximum power spectrum among frequency components of the first and the second in-phase complex signal, and a second peak frequency giving a maximum power spectrum among frequency components of the first and the second quadrature-phase complex signal.
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