The PLL (Phase Lock Loop) circuit generates a sampling clock for sampling an analog image signal and a second clock having a frequency equal to that of the sampling clock and a phase different from that of the sampling clock based on the horizontal synchronizing signal supplied together with the analog image signal. The measuring circuit counts the number of pulses of the sampling clock and the number of pulses of the second clock for a predetermined time period. The MPU (Micro Processing Unit) determines whether or not the numbers of pulses of the sampling clock and second clock have been counted correctly based on the number of pulses of the sampling clock and the number of pulses of the second clock. Then, the MPU adjusts the frequency and phase of the sampling clock, when it is determined that the numbers have been counted correctly.