发明授权
US06504207B1 Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same
失效
创建集成了高性能逻辑和NVRAM的EEPROM存储器结构的方法,以及与之相同的操作条件
- 专利标题: Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same
- 专利标题(中): 创建集成了高性能逻辑和NVRAM的EEPROM存储器结构的方法,以及与之相同的操作条件
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申请号: US09609292申请日: 2000-06-30
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公开(公告)号: US06504207B1公开(公告)日: 2003-01-07
- 发明人: Bomy A. Chen , Jay G. Harrington , Kevin M. Houlihan , Dennis Hoyniak , Chung Hon Lam , Hyun Koo Lee , Rebecca D. Mih , Jed H. Rankin
- 申请人: Bomy A. Chen , Jay G. Harrington , Kevin M. Houlihan , Dennis Hoyniak , Chung Hon Lam , Hyun Koo Lee , Rebecca D. Mih , Jed H. Rankin
- 主分类号: H01L2976
- IPC分类号: H01L2976
摘要:
A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.
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