An apparatus and method for hardware logic verification data transfer checking are implemented. Data for transfer is generated in response to a decoded bus transaction instruction using a pseudorandom number generator. The seed for the generator includes a predetermined portion provided to each bus device. The predetermined portion is combined with the address of the target device, obtained from the decoded instruction, to form the seed input to the random number generator. For write transactions, the bus master generates the data to be transferred using the seed, and sends the data to the target. The target independently generates the data by a call to the random number generator and compares the value received via the data transfer with the independently generated value. Similarly, for read transactions, the slave device generates the data to be transferred in response to the read request. The bus master initiating the read independently generates the data value by a call to the pseudorandom number generator, and effects the comparison between the received and independently generated values. If a miscompare occurs, for a bus transaction, a data transfer error has occurred, and is reported.