发明授权
US06507938B1 Methods for improving the performance of VLSI layouts designed by a timing driven physical design tool
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用于提高由时序驱动的物理设计工具设计的VLSI布局的性能的方法
- 专利标题: Methods for improving the performance of VLSI layouts designed by a timing driven physical design tool
- 专利标题(中): 用于提高由时序驱动的物理设计工具设计的VLSI布局的性能的方法
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申请号: US09439877申请日: 1999-11-12
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公开(公告)号: US06507938B1公开(公告)日: 2003-01-14
- 发明人: Kalapi Roy-Neogi , Nanda Gopal
- 申请人: Kalapi Roy-Neogi , Nanda Gopal
- 主分类号: G06F1750
- IPC分类号: G06F1750
摘要:
Methods for improving the performance of VLSI layouts designed by a timing driven physical design tool. According to one embodiment of the present invention cells of a circuit design are placed in a placement of an integrated circuit, and wires are routed between the cells to complete a layout of the integrated circuit having a number of nets. The placement is analyzed for timing performance, and an improved location is identified for each cell in the placement. The improved location is identified based on an estimated savings in delays caused by all of the nets in the layout to a signal propagating through the layout when the cell is placed in the improved location and a net criticality of each net in the layout.
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