A system is described for prefetching data from a main memory before the data is requested by a processor. The system includes a prefetch buffer having a number of entries to store prefetch reads. Each entry in the prefetch buffer includes a storage area designated for data and address. The system also includes a number of state machines, each state machine to track data phase for each entry in the prefetch buffer. A read request controller is coupled to the prefetch buffer and is configured to receive a read request from the processor or I/O devices and controls dispatching of prefetch requests to a main memory.