发明授权
US06528855B2 MOSFET having a low aspect ratio between the gate and the source/drain
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MOSFET在栅极和源极/漏极之间具有低的纵横比
- 专利标题: MOSFET having a low aspect ratio between the gate and the source/drain
- 专利标题(中): MOSFET在栅极和源极/漏极之间具有低的纵横比
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申请号: US09911894申请日: 2001-07-24
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公开(公告)号: US06528855B2公开(公告)日: 2003-03-04
- 发明人: Qiuyi Ye , William Tonti , Yujun Li , Jack A. Mandelman
- 申请人: Qiuyi Ye , William Tonti , Yujun Li , Jack A. Mandelman
- 主分类号: H01L29772
- IPC分类号: H01L29772
摘要:
A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.
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