The invention relates to a power MOSFET and reduction of the number of mask steps in a process of fabricating the power MOSFET. The increase of a parasitic capacitance due to the reduction is suppressed. In place of a thick insulating film 3, a gate insulating film 12 is formed on the entire surface of a semiconductor substrate. The gate-drain parasitic capacitance which uses the gate insulating film as a dielectric is suppressed by forming a removal region EL.