发明授权
US06537908B2 Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask
失效
使用旋转分布式硬掩模的低k互连的双重磁阻图案化方法
- 专利标题: Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask
- 专利标题(中): 使用旋转分布式硬掩模的低k互连的双重磁阻图案化方法
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申请号: US09795417申请日: 2001-02-28
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公开(公告)号: US06537908B2公开(公告)日: 2003-03-25
- 发明人: Ann Rhea-Helene Fornof , Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Christy Sensenich Tyberg
- 申请人: Ann Rhea-Helene Fornof , Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Christy Sensenich Tyberg
- 主分类号: H01L214763
- IPC分类号: H01L214763
摘要:
A cost effective and simple method of patterning interconnect structures is provided in which spun-on materials are used as the hard mask. The use of spun-on materials for the hard mask ensures that the process is carried out in a single tool and it permits the use of a single curing step which is not typically employed in patterning processes wherein CVD hard masks are employed. The effective dielectric constant of the resultant structure is not significantly increased since the use of spin coating allows for selection of a polish stop layer (formed on a surface of a low-k dielectric) that has substantially the same dielectric constant as the underlying dielectric. In the present invention, the hard mask employed includes at least two spun-on dielectric materials that have different etch rates.
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