发明授权
- 专利标题: System and method for TLB buddy entry self-timing
- 专利标题(中): TLB伙伴进入自我定时的系统和方法
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申请号: US09510276申请日: 2000-02-21
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公开(公告)号: US06539466B1公开(公告)日: 2003-03-25
- 发明人: Reid James Riedlinger
- 申请人: Reid James Riedlinger
- 主分类号: G06F1210
- IPC分类号: G06F1210
摘要:
A self-timed translation lookaside buffer (TLB) is disclosed that utilizes a two-level match scheme to trigger the evaluation of whether a match is achieved for a received virtual address within the TLB. The first level is referred to as the local match, and the second level is referred to as the global match. An entry of a TLB comprises groups of bits, with each group coupled to a separate local match line. Each of the local match lines of an entry is coupled to a global match line, which is initially set to a high voltage level and discharges to a low voltage level if any of the local match lines indicate a mismatch for their respective group. Accordingly, when the global match lines are evaluated, if the global match line has a high voltage level it indicates that the associated TLB entry matches the virtual address, otherwise the global match line indicates a mismatch for the entry. Multiple global match lines are evaluated to trigger a memory access for a matching entry. More specifically, in a preferred embodiment, a pair of neighboring global match lines are input to a NAND gate, the output of which triggers the evaluation of whether a match is achieved for either entry.
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