发明授权
US06541327B1 Method to form self-aligned source/drain CMOS device on insulated staircase oxide
失效
在绝缘阶梯氧化物上形成自对准源极/漏极CMOS器件的方法
- 专利标题: Method to form self-aligned source/drain CMOS device on insulated staircase oxide
- 专利标题(中): 在绝缘阶梯氧化物上形成自对准源极/漏极CMOS器件的方法
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申请号: US09760123申请日: 2001-01-16
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公开(公告)号: US06541327B1公开(公告)日: 2003-04-01
- 发明人: Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
- 申请人: Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
- 主分类号: H01L218238
- IPC分类号: H01L218238
摘要:
A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.
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