Semiconductor memory device performing high speed coincidence comparison operation with defective memory cell address

发明授权

US06542422B1 Semiconductor memory device performing high speed coincidence comparison operation with defective memory cell address 失效

标题翻译：半导体存储器件执行具有缺陷存储单元地址的高速一致比较操作

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专利标题： Semiconductor memory device performing high speed coincidence comparison operation with defective memory cell address
专利标题（中）： 半导体存储器件执行具有缺陷存储单元地址的高速一致比较操作
申请号： US10246455

申请日： 2002-09-19
公开(公告)号： US06542422B1

公开(公告)日： 2003-04-01
发明人: Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo
申请人： Kiyohiro Furutani , Takeshi Hamamoto , Takashi Kubo
优先权： JP2002-105369 20020408
主分类号： G11C700
IPC分类号： G11C700

Semiconductor memory device performing high speed coincidence comparison operation with defective memory cell address

摘要：

When an inputted column address CA and a defect address are compared with each other, an preset defect address and a defect conversion address obtained by inverse conversion of the defect address are both inputted to a comparison circuit. In the comparison circuit, coincidence determination operations are performed being switched between when address conversion is applied to the column address CA and when no address conversion is applied thereto, thereby coincidence comparison can be effected without using the column address CA after an address conversion operation; therefore, a delay in a determination operation accompanying a conversion operation is canceled to perform high speed data reading.

摘要（中）：

当将输入的列地址CA和缺陷地址相互比较时，通过对缺陷地址进行逆转换而获得的预设缺陷地址和缺陷转换地址都被输入到比较电路。在比较电路中，在将地址转换应用于列地址CA之间进行切换时，并且当不对其进行地址转换时进行重合确定操作，从而可以在地址转换操作之后不使用列地址CA来实现一致比较; 因此，取消伴随转换操作的确定操作的延迟以执行高速数据读取。

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