发明授权
- 专利标题: Read port design and method for register array
- 专利标题(中): 读端口设计和寄存器阵列的方法
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申请号: US09955619申请日: 2001-09-18
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公开(公告)号: US06542423B1公开(公告)日: 2003-04-01
- 发明人: Vydhyanathan Kalyanasundharam , Ajay Naini
- 申请人: Vydhyanathan Kalyanasundharam , Ajay Naini
- 主分类号: G11C700
- IPC分类号: G11C700
摘要:
A register array system including a first number of rows by a second number of columns of data registers, a read line, a read bit line, and a single pull down device corresponding to each data register in each column of data registers and configured to discharge, in response to being turned on, the read bit line corresponding to the column of data registers. The pull down device corresponding to a data register is only turned in response to a clock signal, a read enable signal, and the data stored in the data register each having a high value. Therefore, the capacitance associated with the read bit line corresponding to a column of data registers stays at the same capacitance value during the precharging phase and during a multi-hot condition. The problem of voltage droop caused by charging sharing in a multi-hot condition is thus eliminated.
公开/授权文献
- US20030058718A1 READ PORT DESIGN AND METHOD FOR REGISTER ARRAY 公开/授权日:2003-03-27
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