A method and circuitry for linearly delaying a signal with linear delay steps. In one embodiment, circuitry in an integrated circuit for linearly delaying a signal comprises a plurality of control signals. The circuitry further comprises a fine delay element coupled to at least one of the plurality of control signals where the fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of the signal. The circuitry further comprises at least one course delay element coupled to the fine delay element where the at least one course delay element is coupled to at least one of the plurality of control signals. Furthermore, the at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of the signal. The circuitry for linearly delaying a signal is configured to provide testability and programmability. The circuitry for linearly delay a signal is configured to provide linear delay steps. In another embodiment of the present invention, a test signal is coupled to the fine delay element and to the at least one course delay element. The test signal is used to detect faults at the fine delay element and at the at least one course delay element. During the functional mode of this embodiment, power is reduced by disconnecting the test path during the functional mode.