发明授权
- 专利标题: Method for efficient analysis semiconductor failures
- 专利标题(中): 有效分析半导体故障的方法
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申请号: US09511169申请日: 2000-02-24
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公开(公告)号: US06553521B1公开(公告)日: 2003-04-22
- 发明人: Dieter Rathei , Thomas Giegold , Joerg Wohlfahrt
- 申请人: Dieter Rathei , Thomas Giegold , Joerg Wohlfahrt
- 主分类号: G11C2900
- IPC分类号: G11C2900
摘要:
The present invention includes a method for characterizing semiconductor failure. The method includes determining the dimensions of certain characteristics of a memory chip. The method defines a group of characteristics for a semiconductor of given dimensions. The method defines a ratio based on variables supplied by production test systems. By comparing a set of characteristics for a specific semiconductor to the ratio to determine the dominant type of failure on the semiconductor chip. The invention is an efficient method of obtaining information regarding the types of failures common on semiconductor chips.
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