Invention Grant
- Patent Title: Dynamic memory circuit including spare cells
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Application No.: US09895026Application Date: 2001-06-29
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Publication No.: US06563749B2Publication Date: 2003-05-13
- Inventor: Richard Ferrant
- Applicant: Richard Ferrant
- Priority: FR008498 20000630
- Main IPC: G11C700
- IPC: G11C700

Abstract:
A dynamic memory circuit including memory cells arranged in an array of rows and columns, each row capable of being activated by a word line and each column being formed of cells connected to a first and to a second bit lines, which includes at least one, spare row formed of static memory cells, adapted to being activated to replace a memory cell row, each spare cell being connected to the first and second bit lines of a column of the circuit.
Public/Granted literature
- US20020001242A1 Dynamic memory circuit including spare cells Public/Granted day:2002-01-03
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