发明授权
US06564297B1 Compiler-based cache line optimization 有权
基于编译器的缓存行优化

  • 专利标题: Compiler-based cache line optimization
  • 专利标题(中): 基于编译器的缓存行优化
  • 申请号: US09594430
    申请日: 2000-06-15
  • 公开(公告)号: US06564297B1
    公开(公告)日: 2003-05-13
  • 发明人: Nicolai Kosche
  • 申请人: Nicolai Kosche
  • 主分类号: G06F1202
  • IPC分类号: G06F1202
Compiler-based cache line optimization
摘要:
Cache line optimization involves computing where cache misses are in a control flow and assigning probabilities to cache misses. Cache lines may be scheduled based on the assigned probabilities and where the cache misses are in the control flow. Cache line probabilities may be calculated based on the relationship of the cache line and where the cache misses are in the control flow. A control flow may be pruned before calculating cache line probabilities. Function call sites may be used to prune the control flow. Address generation of a cache miss may be duplicated to speculatively hoist address generation and the associated prefetch. References may be selected for optimization, identifying cache lines, and mapping the selected references. Dependencies within the cache lines may be determined and the cache lines may be scheduled based on the determined dependencies and probabilities of usefulness. Instructions may be scheduled based on the scheduled cache lines and the target machine model to maximize outstanding memory transactions. Cache lines may be scheduled across call sites.
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