Invention Grant
- Patent Title: High voltage transistor using P+ buried layer
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Application No.: US10091990Application Date: 2002-03-06
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Publication No.: US06569730B2Publication Date: 2003-05-27
- Inventor: Jun-Lin Tsai , Ruey-Hsin Liu , Jei-Feng Hwang , Kuo-Chio Liu
- Applicant: Jun-Lin Tsai , Ruey-Hsin Liu , Jei-Feng Hwang , Kuo-Chio Liu
- Main IPC: H01L218249
- IPC: H01L218249

Abstract:
A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.
Public/Granted literature
- US20020105054A1 High voltage transistor using P+ buried layer Public/Granted day:2002-08-08
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