- 专利标题: Semiconductor memory having refresh function
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申请号: US09981517申请日: 2001-10-16
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公开(公告)号: US06570801B2公开(公告)日: 2003-05-27
- 发明人: Munehiro Yoshida , Hiroshi Shinya
- 申请人: Munehiro Yoshida , Hiroshi Shinya
- 优先权: JP2000-329264 20001027
- 主分类号: G11C700
- IPC分类号: G11C700
摘要:
An internal row address signal is generated by a refresh address counter and supplied to a row decoder. In a normal refresh operation, the refresh address counter sequentially increments the internal row address signal on the basis of a trigger signal. As a result, the data in all memory cells is refreshed. In a low-consumption-current refresh operation, at least one of the bits of the internal row address signal is fixed. Hence, the refresh operation is executed only for the memory cells of a predetermined refresh area.
公开/授权文献
- US20020074568A1 Semiconductor memory having refresh function 公开/授权日:2002-06-20