A channel layer 4 is formed on an n−-type epitaxial layer 2 and first gate areas 3, and field enhanced area(s) 5 and second gate areas 6 are formed on the first gate areas 3. Furthermore, n+-type source areas 7 and a third gate area 8 are formed on the second gate areas 6. These steps result in a device structure having a first J-FET with the n+-type source areas 7 and the n+-type substrate 1 as a source and drain and the first gate areas 3 at the right and left in the figure as a gate; and the second J-FET with the n+-type source areas 7 and the n+-type substrate 1 as a source and drain and the second gate areas 6 and the third gate area 8 as a gate. The first J-FET is normally-on, while the second J-FET is normally-off.