Dual chip in package with a wire bonded die mounted to a substrate

发明授权

US06586825B1 Dual chip in package with a wire bonded die mounted to a substrate 有权

标题翻译：双芯片封装，带有焊线芯片，安装在基板上

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专利标题： Dual chip in package with a wire bonded die mounted to a substrate
专利标题（中）： 双芯片封装，带有焊线芯片，安装在基板上
申请号： US09843443

申请日： 2001-04-26
公开(公告)号： US06586825B1

公开(公告)日： 2003-07-01
发明人: Sarathy Rajagopalan , Kishor Desai , Maniam Alagaratnam
申请人： Sarathy Rajagopalan , Kishor Desai , Maniam Alagaratnam
主分类号： H05K116
IPC分类号： H05K116

Dual chip in package with a wire bonded die mounted to a substrate

摘要：

A package comprises a top die and a bottom die. The top die has top and bottom surfaces while the bottom die has top and bottom surfaces. The bottom die is mounted on a substrate, which has a top surface, such that the bottom surface of the bottom die faces the top surface of the substrate. The bottom surface of the top die is separated from the top surface of the bottom die by an interposer, which creates a space between the exterior regions of the top surface of the bottom die and the bottom surface of the top die. Each of a plurality of wires, which are electrically connected to the bottom die, runs through this space (i.e. runs between the top surface of the bottom die and the bottom surface of the top die), thereby permitting (if desired) the top die to be at least as large as the bottom die.

摘要（中）：

包装包括顶模和底模。顶部模具具有顶部和底部表面，而底部模具具有顶部和底部表面。底模安装在具有顶表面的基底上，使得底模的底表面面向基底的顶表面。顶部模具的底表面通过插入件与底模的顶表面分离，其在底模的顶表面的外部区域和顶模的底表面之间产生空间。电连接到底模的多根导线中的每一根穿过该空间（即，在底模的顶表面和顶模的底表面之间延伸），从而允许（如果需要）顶模至少与底部模具一样大。

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