发明授权
- 专利标题: Method of manufacturing dual gate logic devices
- 专利标题(中): 制造双门逻辑器件的方法
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申请号: US09879590申请日: 2001-06-12
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公开(公告)号: US06596597B2公开(公告)日: 2003-07-22
- 发明人: Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma
- 申请人: Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma
- 主分类号: H01L21336
- IPC分类号: H01L21336
摘要:
The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching germanium-containing gate conductor materials without significantly etching the adjacent silicon channel material. In this manner, the gate conductor can be encased in a dielectric shell without changing the length of the silicon channel. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack. A process is described wherein the gate conductor material can be selectively etched without etching the channel material.
公开/授权文献
- US20020187610A1 Dual gate logic device 公开/授权日:2002-12-12