Invention Grant
US06596609B2 Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer 有权
使用两个边缘限定层和间隔物在集成电路中制造特征的方法

  • Patent Title: Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer
  • Patent Title (中): 使用两个边缘限定层和间隔物在集成电路中制造特征的方法
  • Application No.: US09740782
    Application Date: 2000-12-19
  • Publication No.: US06596609B2
    Publication Date: 2003-07-22
  • Inventor: Peng ChengBrian S. Doyle
  • Applicant: Peng ChengBrian S. Doyle
  • Main IPC: H01L21265
  • IPC: H01L21265
Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer
Abstract:
A method of fabricating a feature on a substrate is disclosed. In a described embodiment the feature is the gate electrode of an MOS transistor. In this embodiment a polysilicon layer is formed on the substrate. Next, an edge definition layer of silicon nitride is formed on the feature layer. Then, a patterned edge definition layer of silicon dioxide is formed on the first edge definition layer. Then, a silicon nitride spacer is formed adjacent to an edge of the patterned second edge definition layer. Finally, the polysilicon layer is etched, forming the transistor gate electrode from the polysilicon that remains under the spacer.
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