A DA converting circuit comprises a first DA converter (12) for outputting an analog voltage corresponding to a value of a digital input signal, and a calibration mechanism (11, 13, 14, 15, 16 and 17) for generating a correction signal to cancel an offset related to a conversion operation by the converter. The calibration mechanism includes a correction value setting section (14, 15 and 16) for generating a digital correction value to cancel an offset, a second DA converter (17) to convert the digital correction value generated in the correction value setting section into an analog voltage, and an analog adder (13) to add together an analog voltage supplied by the second converter and an analog voltage supplied by the first converter, and outputs an analog output signal value representing the result of addition.