• 专利标题: Semiconductor wafer test system
  • 申请号: US09905922
    申请日: 2001-07-17
  • 公开(公告)号: US06603316B2
    公开(公告)日: 2003-08-05
  • 发明人: Hideo Oishi
  • 申请人: Hideo Oishi
  • 优先权: JP2000-215312 20000717
  • 主分类号: H01H3112
  • IPC分类号: H01H3112
Semiconductor wafer test system
摘要:
A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates an ac electric field to be placed on the devices. The ac field should have an intensity at least equal to a minimum value required for the burn-in test and less than a critical value, below which no breakdown occurs in the gate oxide film of each device. By changing the amount of time for which the devices are exposed to the ac field, the burn-in period can be changed freely. In addition, forward and reverse fields are both placed on the gate oxide film of each device. Thus, failures can be screened out very effectively.
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