发明授权
US06604189B1 Master/slave processor memory inter accessability in an integrated embedded system
失效
主/从处理器存储器在集成嵌入式系统中的可访问性
- 专利标题： Master/slave processor memory inter accessability in an integrated embedded system
- 专利标题（中）： 主/从处理器存储器在集成嵌入式系统中的可访问性
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申请号： US09576575申请日： 2000-05-22
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公开(公告)号： US06604189B1公开(公告)日： 2003-08-05
- 发明人: Boris Zemlyak , Ariel Cohen
- 申请人： Boris Zemlyak , Ariel Cohen
- 主分类号： G06F15163
- IPC分类号： G06F15163
摘要：
An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The one or more first processors may be configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in the one or more first RAM sections. The one or more second processors may be configured to execute code from either (i) the one or more ROM sections or (ii) the one or more second RAM sections. The apparatus may provide interoperability that may increase system observability and decrease system debugging complexity.
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