Invention Grant
- Patent Title: Semiconductor device having gate all around type transistor and method of forming the same
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Application No.: US10039151Application Date: 2002-01-03
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Publication No.: US06605847B2Publication Date: 2003-08-12
- Inventor: Sang-Su Kim , Tae-Hee Choe , Hwa-Sung Rhee , Geum-Jong Bae , Nae-In Lee
- Applicant: Sang-Su Kim , Tae-Hee Choe , Hwa-Sung Rhee , Geum-Jong Bae , Nae-In Lee
- Priority: KR2001-19525 20010412
- Main IPC: H01L29786
- IPC: H01L29786

Abstract:
A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.
Public/Granted literature
- US20020149031A1 Semiconductor device having gate all around type transistor and method of forming the same Public/Granted day:2002-10-17
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