发明授权
- 专利标题: Semiconductor intergrated circuit device and a method of manufacture thereof
- 专利标题(中): 半导体集成电路器件及其制造方法
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申请号: US09592648申请日: 2000-06-13
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公开(公告)号: US06621110B1公开(公告)日: 2003-09-16
- 发明人: Hideyuki Matsuoka , Satoru Yamada , Isamu Asano , Ryo Nagai , Tomonori Sekiguchi , Riichiro Takemura
- 申请人: Hideyuki Matsuoka , Satoru Yamada , Isamu Asano , Ryo Nagai , Tomonori Sekiguchi , Riichiro Takemura
- 优先权: JP11-166320 19990614
- 主分类号: H01L27108
- IPC分类号: H01L27108
摘要:
A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.
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