发明授权
US06628001B1 Integrated circuit die having alignment marks in the bond pad region and method of manufacturing same
有权
具有接合焊盘区域中的对准标记的集成电路管芯及其制造方法
- 专利标题： Integrated circuit die having alignment marks in the bond pad region and method of manufacturing same
- 专利标题（中）： 具有接合焊盘区域中的对准标记的集成电路管芯及其制造方法
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申请号： US10150790申请日： 2002-05-17
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公开(公告)号： US06628001B1公开(公告)日： 2003-09-30
- 发明人: Sailesh Chittipeddi , Keelathur N. Vasudevan
- 申请人： Sailesh Chittipeddi , Keelathur N. Vasudevan
- 主分类号： H01L23544
- IPC分类号： H01L23544
摘要：
The present invention provides a die located on a semiconductor wafer. In one embodiment, the die includes a circuit region located within a circuit perimeter of the die. In addition, the die includes a bond pad region located between the circuit perimeter and an outer perimeter of the die. Also the die includes an alignment mark located within the bond pad region.