An apparatus includes a memory buffer, a first signal buffer, a locked loop circuit and a feedback circuit. The memory buffer provides a data signal to an output terminal of the memory buffer in response to a first clock signal. The first signal buffer is coupled between the output terminal of the memory buffer and a data line of a bus. The first signal buffer introduces a first delay. The locked loop circuit furnishes the first clock signal to establish a predefined relationship between a phase of a second clock signal and a phase of a third clock signal. The feedback circuit produces the second clock signal in response to the first clock signal. The feedback circuit includes a second signal buffer to introduce a second delay to the second clock, and the second delay is approximately the same as the first delay that is introduced by the first signal buffer.