发明授权
US06631474B1 System to coordinate switching between first and second processors and to coordinate cache coherency between first and second processors during switching 有权
用于协调第一和第二处理器之间的切换以及在切换期间协调第一和第二处理器之间的高速缓存一致性的系统

  • 专利标题: System to coordinate switching between first and second processors and to coordinate cache coherency between first and second processors during switching
  • 专利标题(中): 用于协调第一和第二处理器之间的切换以及在切换期间协调第一和第二处理器之间的高速缓存一致性的系统
  • 申请号: US09476038
    申请日: 1999-12-31
  • 公开(公告)号: US06631474B1
    公开(公告)日: 2003-10-07
  • 发明人: Zhong-Ning George CaiTosaku Nakanishi
  • 申请人: Zhong-Ning George CaiTosaku Nakanishi
  • 主分类号: G06F126
  • IPC分类号: G06F126
System to coordinate switching between first and second processors and to coordinate cache coherency between first and second processors during switching
摘要:
A computer system includes a first processor, a second processor, and interprocessor communication logic (ICL). The first processor operates at a higher frequency, includes a more advanced micro-architecture, and consumes more power than the second processor. When the computer system is plugged in, the first processor is selected as the primary system processor. When the computer system is powered by a battery, the second processor is selected as the primary system processor. The second processor and the ICL may be integrated together on the same semiconductor chip.
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