The system and method of the present invention is embodied in a multi-state on-chip logic analyzer that is preferably integrated into a VLSI circuit. In general, the logic analyzer is preferably coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. The logic analyzer has the capability match one or more programmable trigger events to satisfy one or more programmable conditions. Further, the logic analyzer preferably has the capability to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis. Trace array input and output logic allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. Further, the trace array input and output logic is preferably accessible at both the wafer and component stage to allow for testing and debugging of the VLSI circuitry.