发明授权
US06634012B2 Design verification by symbolic simulation using a native hardware description language
有权
使用本机硬件描述语言通过符号仿真进行设计验证
- 专利标题： Design verification by symbolic simulation using a native hardware description language
- 专利标题（中）： 使用本机硬件描述语言通过符号仿真进行设计验证
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申请号： US09395873申请日： 1999-09-14
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公开(公告)号： US06634012B2公开(公告)日： 2003-10-14
- 发明人: John Xiaoxiong Zhong , Dian Yang , Zheng Zhou , Ting Wang
- 申请人： John Xiaoxiong Zhong , Dian Yang , Zheng Zhou , Ting Wang
- 主分类号： G06F945
- IPC分类号： G06F945
摘要：
A method and apparatus for performing design verification is described. In one embodiment, a method for performing design verification includes specifying at least one object that represents at least one signal as a symbol in a design using a first command and instructing a symbolic simulator with the first command to treat the at least one object as a symbol.
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