Invention Grant
- Patent Title: Method of forming a MOS transistor in a semiconductor device and a MOS transistor fabricated thereby
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Application No.: US10228060Application Date: 2002-08-27
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Publication No.: US06635522B2Publication Date: 2003-10-21
- Inventor: Jae-Kyu Lee , Jae-Goo Lee
- Applicant: Jae-Kyu Lee , Jae-Goo Lee
- Priority: KR99-53878 19991130
- Main IPC: H01L218238
- IPC: H01L218238

Abstract:
Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region of the semiconductor substrate of a first conductivity type so that portions of the semiconductor substrate of a first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern. The MOS transistor also includes impurity regions having at least an upper surface of a second conductivity type disposed on the semiconductor substrate at at least one side of the insulated gate pattern, as well as at least one spacer disposed on at least one sidewall of the insulated gate pattern. The MOS transistor further contains a pad of a second conductivity type disposed on an upper surface of the impurity regions, whereby the pad covers a lower portion of the at least one spacer.
Public/Granted literature
- US20020195666A1 Method of forming a MOS transistor in a semiconductor device and a MOS transistor fabricated thereby Public/Granted day:2002-12-26
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