A system includes a processor and a flash memory block that may receive an operating voltage sufficient for reading a memory cell. A standby oscillator may generate a first signal to a Power-Supply-In-Package block and a second, higher frequency signal to a regulator block. The first signal may control the time at which charge is stored on a first capacitor that may be used to provide charge in a standby mode to a second capacitor. The second signal may control the time at which charge is stored on the second capacitor.