发明授权
US06642590B1 Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process 有权
具有PVD非晶硅层的金属栅极和用于CMOS器件的阻挡层以及用替代栅极工艺制造的方法

  • 专利标题: Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process
  • 专利标题(中): 具有PVD非晶硅层的金属栅极和用于CMOS器件的阻挡层以及用替代栅极工艺制造的方法
  • 申请号: US09691227
    申请日: 2000-10-19
  • 公开(公告)号: US06642590B1
    公开(公告)日: 2003-11-04
  • 发明人: Paul R. BesserQi XiangMatthew S. Buynoski
  • 申请人: Paul R. BesserQi XiangMatthew S. Buynoski
  • 主分类号: H01L2976
  • IPC分类号: H01L2976
Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process
摘要:
A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. A barrier layer is deposited on the PVD amorphous silicon layer. The metal is then formed on the barrier layer. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer. The barrier layer prevents interaction between the PVD amorphous silicon layer and the metal, thereby allowing higher temperature subsequent processing while preserving the work function of the gate.
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