A digital signal processor (DSP) of high speed and high precision is disclosed. The DSP (i.e., digital arithmetic integrated circuit) comprises: an arithmetic data storing memory (11) for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string being composed of m-bits of at least a predetermined unit word length and the second arithmetic data string being composed of (m×n)-bits of a unit word length; two arithmetic operand storing registers (12) for storing the first and second arithmetic data strings outputted by said arithmetic data storing memory, respectively; an arithmetic logical unit for executing arithmetic operation on the basis of the two operands outputted by said arithmetic operand storing registers in one instruction cycle (13); and an arithmetic result storing register (15) for storing the arithmetic results outputted by said arithmetic logical unit.