The invention teaches how to reduce the traffic associated with handling cache lines containing useless data (i.e. cache lines corresponding to pages that have been invalidated). The invention makes it possible to evict such cache lines earlier, to avoid write backs of useless data from such cache lines to main memory, and to avoid transmitting useless data from such cache lines to the requesting remote coherence controller in a multiprocessor system. The present invention describes a mechanism for invalidating cache lines containing useless data transparently and without programmer's involvement. For efficiency, the content of a cache line containing useless data is invalidated only when the line is referenced or is about to be allocated for some new data.