发明授权
US06643768B2 Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder
失效
具有从每组乘法器和加法器中选择的主和子操作功能块的Dyadic DSP指令处理器
- 专利标题： Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder
- 专利标题（中）： 具有从每组乘法器和加法器中选择的主和子操作功能块的Dyadic DSP指令处理器
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申请号： US10216044申请日： 2002-08-09
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公开(公告)号： US06643768B2公开(公告)日： 2003-11-04
- 发明人: Kumar Ganapathy , Ruban Kanapathipillai
- 申请人： Kumar Ganapathy , Ruban Kanapathipillai
- 主分类号： G06F9302
- IPC分类号： G06F9302
摘要：
A dyadic digital signal processing (DSP) instruction processor including a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to execute a sub operation of the dyadic DSP instruction with data paths of each selectively configured to execute the main operation and the sub operation of the dyadic DSP instruction. A voice and data communication system has a first gateway and a second gateway coupled to a packetized network, each gateway having a network interface including the dyadic DSP instruction processor. An application specific signal processor with a signal processor having a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to execute a sub operation with multiplexers coupled to the first DSP functional block and the second DSP functional block to selectively configure data paths thereto.
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