Invention Grant
- Patent Title: Double precision floating point multiplier having a 32-bit booth-encoded array multiplier
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Application No.: US10217740Application Date: 2002-08-12
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Publication No.: US06647404B2Publication Date: 2003-11-11
- Inventor: Tzungren Allan Tzeng , Choon Ping Chng
- Applicant: Tzungren Allan Tzeng , Choon Ping Chng
- Main IPC: G06F752
- IPC: G06F752

Abstract:
A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.
Public/Granted literature
- US20030005016A1 Double precision floating point multiplier having a 32-bit booth-encoded array multiplier Public/Granted day:2003-01-02
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