发明授权
US06651144B1 Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty state
失效
用于使用外部确认信号开发多处理器高速缓存控制协议以将高速缓存设置为脏状态的方法和装置
- 专利标题: Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty state
- 专利标题(中): 用于使用外部确认信号开发多处理器高速缓存控制协议以将高速缓存设置为脏状态的方法和装置
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申请号: US09099384申请日: 1998-06-18
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公开(公告)号: US06651144B1公开(公告)日: 2003-11-18
- 发明人: Rahul Razdan , James B. Keller , Richard E. Kessler
- 申请人: Rahul Razdan , James B. Keller , Richard E. Kessler
- 主分类号: G06F1200
- IPC分类号: G06F1200
摘要:
A computer system includes an external unit governing a cache which generates a set-dirty request as a function of a coherence state of a block in the cache to be modified. The external unit modifies the block of the cache only if an acknowledgment granting permission is received from a memory management system responsive to the set-dirty request. The memory management system receives the set-dirty request, determines the acknowledgment based on contents of the plurality of caches and the main memory according to a cache protocol and sends the acknowledgment to the external unit in response to the set-dirty request. The acknowledgment will either grant permission or deny permission to set the block to the dirty state.
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