发明授权
US06657967B1 Dummy bit elimination device and coding apparatus for FEC code word
失效
用于FEC码字的伪位消除装置和编码装置
- 专利标题: Dummy bit elimination device and coding apparatus for FEC code word
- 专利标题(中): 用于FEC码字的伪位消除装置和编码装置
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申请号: US09285775申请日: 1999-04-05
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公开(公告)号: US06657967B1公开(公告)日: 2003-12-02
- 发明人: Takanori Fujisawa , Kenichi Nomura , Yasushi Hara , Norio Yanagi , Hiroaki Tanaka
- 申请人: Takanori Fujisawa , Kenichi Nomura , Yasushi Hara , Norio Yanagi , Hiroaki Tanaka
- 优先权: JP10-093273 19980406
- 主分类号: H04J314
- IPC分类号: H04J314
摘要:
A dummy bit elimination device in a coding apparatus for use in a submarine cable system. The dummy bit elimination device has a converter for eliminating only dummy bits from FEC (Forward Error Correction) code. The coding apparatus has an optical-to-electrical signal transducer, a demultiplexer, a coder for generating an FEC code, a multiplexer for multiplexing inputs, and an electrical-to-optical signal transducer. The dummy bit elimination device is inserted between the coder and the multiplexer so that the outputs of the coder are fed to the converter and an outputs of the converter are fed to the multiplexer.