Serial interface circuits include first and second data registers (RXDR, TXDR) responsive to first and second register control signals (Idrd, Idts), respectively, and a shift register (SISOR) responsive to a shift clock signal. The preferred shift register has a serial input port, a serial output port and a parallel input/output port electrically coupled to the first and second data registers. A preferred controller circuit is also provided. This controller circuit, which is responsive to a frame synchronization signal (Fsync), generates the first and second register control signals during nonoverlapping time intervals. The frame synchronization signal has a first pulse width during a first time interval and the controller circuit also includes a half-frame synchronization signal generator which generates a half-frame synchronization signal (Hlf_Fsync) having a second pulse width during the first time interval. The controller circuit also includes a data register controller to generate the first and second register control signals as respective pulses during the first time interval. The half-frame synchronization signal is preferably generated as a pulse during a second-half of the first time interval and the first and second register control signals are preferably generated as respective pulses during the second-half of the first time interval. If the second-half of the first time interval is defined as a second time interval, then the first register control signal is preferably generated as a pulse during a first-half of the second time interval and the second register control signal is preferably generated as a pulse during a second-half of the second time interval.