An interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the interconnect structure includes a substrate having at least one plated through hole therein, and a first conductive layer sealing the at least one plated through hole. The substrate includes a layer of dielectric material thereon. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, at least a pair of conductive layers that can carry signals, and at least another pair of conductive layers that can carry power, wherein the pair of conductive layers are shielded by the metal layer and the other pair of conductive layers.