- 专利标题: Polishing method and apparatus
-
申请号: US09870479申请日: 2001-06-01
-
公开(公告)号: US06663469B2公开(公告)日: 2003-12-16
- 发明人: Norio Kimura , Tatsuya Kohama
- 申请人: Norio Kimura , Tatsuya Kohama
- 优先权: JP2000-166682 20000602
- 主分类号: B24B719
- IPC分类号: B24B719
摘要:
A semiconductor substrate having a Cu layer formed so as to fill wiring grooves formed in the substrate surface and to cover regions of the substrate surface where no wiring groove is formed is brought into sliding contact with a polishing surface on a turntable to carry out polishing until the Cu layer is polished to a predetermined thickness. Then, the semiconductor substrate is brought into sliding contact with a polishing surface on a turntable to carry out polishing until the Cu layer on the substrate surface is removed, except for portions of the Cu layer formed to fill the wiring grooves, and a barrier metal layer is also removed. Thus, the Cu layer on the substrate surface can be removed uniformly, and the Cu wiring portions formed in the wiring grooves can be planarly and uniformly polished without giving rise to problems of over-polishing such as dishing or erosion.
公开/授权文献
- US20020002029A1 Polishing method and apparatus 公开/授权日:2002-01-03