发明授权
US06671950B2 Multi-layer circuit assembly and process for preparing the same 失效
多层电路组装及其制备方法

  • 专利标题: Multi-layer circuit assembly and process for preparing the same
  • 专利标题(中): 多层电路组装及其制备方法
  • 申请号: US09901373
    申请日: 2001-07-09
  • 公开(公告)号: US06671950B2
    公开(公告)日: 2004-01-06
  • 发明人: Lance C. SturniKevin C. Olson
  • 申请人: Lance C. SturniKevin C. Olson
  • 主分类号: H01K310
  • IPC分类号: H01K310
Multi-layer circuit assembly and process for preparing the same
摘要:
A process for fabricating a multi-layer circuit assembly is provided comprising the following steps: (a) providing a perforate electrically conductive core having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the electrically conductive core to form a conformal coating on all exposed surfaces of the electrically conductive core; (c) ablating the surface of the dielectric coating in a predetermined pattern to expose sections of the electrically conductive core; (d) applying a layer of metal to all surfaces to form metallized vias through the electrically conductive core; and (e) applying a resinous photosensitive layer to the metal layer. Additional processing steps such as circuitization may be included. Also provided are multi-layer circuit assemblies produced by the process of the present invention, comprising component layers having high via density and thermal coefficients of expansion that are compatible with those of semiconductor chips and rigid wiring boards which may be attached as components of the circuit assembly.
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