In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of providing a collar first scheme by forming a high aspect ration PBL SiN barrier, comprising: a) providing a semiconductor structure after SiN node deposition and DT polysilicon fill; b) depositing a poly buffered LOCOS (PBL) Si liner; c) subjecting the PBL liner to oxidation to form a pad oxide and depositing a SiN barrier layer; d) depositing a silicon mask liner; e) subjecting the DT to high directional ion implantation (I/I) using a p-dopant; f) employing a selective wet etch of unimplanted Si with an etch stop on SiN; g) subjecting the product of step f) to a SiN wet etch with an etch stop on the pad oxide; h) affecting a Si liner etch with a stop on the pad oxide; i) oxidizing the PBL Si liner and affecting a barrier SiN strip; j) providing a DT polysilicon fill and performing a poly chemical mechanical polishing.