A semiconductor memory device including a plurality of cell arrays (121 to 128) and a plurality of sense amplifier sections is disclosed. Adjacent cell arrays may have a sense amplifier section disposed between. Sense amplifiers (131 to 163) within a sense amplifier section may be connected to a bit line that is connected to a plurality of memory cells in more than one of the cell arrays (121 to 128). When a cell array (123) is activated, sense amplifier sections that may be distributed around edges of a plurality of cell arrays (122 to 124) may be activated to sense data from the activated cell array (123). In this way, current may be distributed and noise may be reduced. An activated bit line (227) may be adjacent to a precharged bit line (250) in a non-activated cell array (124). In this way, cross-talk between activated bit lines may be reduced.